1. Field of the Invention
The invention relates to a thin film capacitor formed on a semiconductor substrate, and a method of fabricating the same.
2. Description of the Related Art
A conventional thin film capacitor used in a semiconductor integrated circuit such as a dynamic random access memory (DRAM) is generally designed to have a multi-layered structure including upper and lower electrodes composed of polysilicon, a silicon dioxide film and a silicon nitride film.
Recently, as an area of a memory cell has been reduced, there has been a demand of reduction in an area of a capacitor. In order to accomplish a high capacitor density which is required in a high-densiity DRAM as a product to be fabricated after 1Gb DRAM and a chip including both DRAM and a logic circuit, it would be necessary to form a quite thin film, which has a silicon dioxide equivalence thickness of 1 mn or smaller.
One of attempts for accomplishing a high capacity is disclosed in 1995 International Electron Devices Meeting Technical Digest, pp. 119-122. In the suggested attempt, a film having a high dielectric constant, such as a film composed of SrTiO.sub.3 having a dielectric constant of about 300 at room temperature or a film composed of (Ba, Sr) TiO.sub.3 having a dielectric constant of 300 or greater, is used as a capacitor insulating film, and a lower electrode is composed of barrier metal such as Pt/Ta or RuO.sub.2 /Ru/TiN/TiSix both of which prevent diffusion of silicon and do not form a layer composed of oxide having a low dielectric constant, even in oxidizing atmosphere established while films having a high dielectric constant are being formed.
There have been reported a lot that it would be possible to fabricate a ferroelectric RAM by using a ferroelectric film composed of ferroelectric substance having ferroelectricity at room temperature, such as Pb (Zr, Ti) O.sub.3, in place of (Ba, Sr) TiO.sub.3.
Electrodes of a thin film capacitor are electrically connected to an electrically conductive layer formed on a semiconductor substrate generally through a contact plug composed of low-resistive contact material filled in a contact hole formed throughout an interlayer insulating film. As the contact material, there is generally used polysilicon into which impurities are doped or tungsten. The contact plug generally has an upper surface which is flat or recessed.
The reason why the upper surface of the contact plug is flat or recessed is derived from a process of fabricating a thin film capacitor. In a conventional process of fabricating a thin film capacitor, a contact hole is first formed throughout an interlayer insulating film, and then, contact material is deposited over the interlayer insulating film to thereby fill the contact hole with the contact material. Thereafter, the contact material is etched back by reactive dry etching or chemical mechanical polishing (CMP) to remove the contact material deposited on the interlayer insulating film. As a result, the contact material filled in the contact hole has an upper surface which is flat or recessed.
If the contact material deposited on the interlayer insulating film is not sufficiently removed, adjacent capacitors would be short-circuited with each other, resulting in malfunction in a circuit. Hence, it is necessary to sufficiently etch the contact material back. As a result, it would be impossible to completely fill the contact hole with the contact material in accordance with dry etching or CMP, resulting in that an upper surface of the contact material filled in the contact hole is flat or recessed.
For instance, a thin film capacitor including a contact plug having a flat upper surface is disclosed in Japanese Unexamined Patent Publications 7-99198, 9-82914, 9-283623, 10-209394 and 10-223848. A thin film capacitor including a contact plug having a recessed upper surface is disclosed, for instance, in Japanese Unexamined Patent Publication No. 10-65001 and Japanese Patent No. 2639355 (Japanese Unexamined Patent Publication No. 8-78519).
A thin film capacitor including a contact plug having a flat or recessed upper surface does not cause any problems while it is being fabricated, but causes a serious problem in annealing steps which are to be carried out when an interlayer insulating film is formed, and then, wiring layers are formed.
For instance, such a serious problem is caused in an annealing step to be carried out at about 400 degrees centigrade in oxygen atmosphere in the case that an interlayer insulating film is composed of O.sub.3 --TEOS/NSG, or in a lamp annealing step to be carried out at 700 degrees centigrade for about 30 seconds for activating impurity ions in the case that aluminum wiring layers are formed.
Herein, the above-mentioned serious problem caused in an annealing step to be carried out after a thin film capacitor has been fabricated is that a lower electrode peels off a contact plug.
A lower electrode in a thin film capacitor is generally comprised of a thin metal film such as Pt/Ta or RuO.sub.2 /Ru/TiN/TiSi both having resistance to oxidation. The thin metal film has a tensile stress when a thin film capacitor is completed. However, if the thin metal film experiences an annealing step at 400 degrees centigrade or greater, a stress in the thin metal film remarkably changes while a temperature is rising, resulting in that a tensile stress is turned into a compressive stress. As a result, the lower electrode comprised of the thin metal film peels off a contact plug composed, for instance, of polysilicon or tungsten.
FIG. 1A illustrates a conventional thin film capacitor, and FIG. 1B illustrates that a lower electrode peels off a contact plug after an annealing step has been carried out.
As illustrated in FIG. 1A, the conventional thin film capacitor is comprised of a silicon substrate 1, an interlayer insulating film 2 formed on the silicon substrate 1, a contact plug 3 filled in a contact hole formed throughout the interlayer insulating film 2, a first lower electrode film 4 formed on the interlayer insulating film 2 covering the contact plug 3, a second lower electrode film 5 formed on the first lower electrode film 4, a capacitor insulating film 6 covering the first and second low electrode films 4 and 5 and the interlayer insulating film 2 therewith, and an upper electrode film 7 formed on the capacitor insulating film 6.
The contact plug 3 in the conventional thin film capacitor has a flat upper surface, as illustrated in FIG. 1A. As mentioned above, a tensile stress is turned into a compressive stress in a part of the first lower electrode film 4 in an annealing step to be carried out after the thin film capacitor has been completed. As a result, a part of the first lower electrode film 4 is upwardly raised, and accordingly, the first lower electrode film 4 peels off the contact plug 3, as indicated with "A" in FIG. 1B.
FIG. 2A illustrates another conventional thin film capacitor, and FIG. 2B illustrates that a lower electrode peels off a contact plug after an annealing step has been carried out.
The contact plug 3 in the thin film capacitor illustrated in FIG. 2A has an upper surface slightly recessed. Hence, a tensile stress in a part of the first lower electrode film 4 is turned into a compressive stress after an annealing step has been carried out, resulting in that the first lower electrode film 4 peels off the contact plug 3, as indicated with "A" in FIG. 2B, in the same way as the thin film capacitor illustrated in FIG. 1A.
If the first lower electrode film 4 peels off the contact plug 3 as illustrated in FIG. 1B, a contact resistance is increased in electrical connection between a transistor formed on the silicon substrate 1 and the thin film capacitor including dielectric substance having a high dielectric constant, resulting in an error such as bit defectiveness in DRAM.